FPGA - Zero to Hero: Vol 2

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In the previous blog I explained how to compile and simulate a basic verilog code using iverilog and gtkwave. Moving on I will be running some verilog code on a real FPGA.

I will be using Altera Cyclone IV FPGA cheap development board. I bought from a Waveshare for $ 50.

I am also using a cheap debugger from Waveshare USB blaster 2Link to program the FPGA.

But you can find this board although smaller number of logic elements and IOs or $10-15 range.

Installation Intel Quartus Prime Lite

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For programming Altera FPGAs you need the toolchain from Intel called Intel Quartus Prime Lite. Link for linux toolchain

I am using linux (Ubuntu 22.04) operating system.For Windows you can just run the .exe

Download the Quartus Installer and make it executable with chmod

chmod +x qinst-lite-linux-23.1std.1-993.run

Run the Installer

./qinst-lite-linux-23.1std.1-993.run

First Program in Intel Quartus Prime Lite

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Create a Project

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You need to create project first. You need to specify the FPGA that you are using and can be found on the list. I am using Altera Cyclone IV EP4CE10F17C8N.

Create the project by clicking new file icon and New Quaruts Prime Project.

A new project wizard will open. Write the name of project you want to create and also specify the directory whre you want to keep it.

I named my project Test. Keep it an Empty Project. Press Next >. For Add Files skip it for now with Next > button. For Family, Device & Board Settings choose your FPGA form the list as shown below for me its Cyclone IV E and EP4CE10F17C8N:

Press Next > and on Summary press Finish button to finish process.

Create a block diagram

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You need to make top file that has all your modules. The easiest way to accomplish it is making a Block Diagram file. First it help to visualize the blocks and it is easier to work with for complex projects

To create block diagram click on new file icon and add a Block Diagram.

If you are following my Raspberry PI blog . I have been trying to get a high speed toggling of the GPIO pins. As Raspberry Pi used in the blog is a sequential processor and with non realtime operating system. Its been very difficult to get that high speed GPIO toggle working there. I will continue that journey in an another blog but for FPGAs it is a piece of cake to toggle GPIO at very high frequency (max frequency depends on many factors i.e. depends on grade of FPGA, type of fpga etc).

Here we will try to test the limits too (Be careful high frequency loading of GPIOs can damage the GPIOs).

USE AT YOUR OWN RISK. The authors code disclaim any and all liability for any direct, indirect, incidental, special, or consequential damages arising out of or in connection with the use, modification, or distribution of this software. This code is provided “AS IS” without any express or implied warranties, including, but not limited to, the implied warranties of merchantability, fitness for a particular purpose, or non-infringement.

Create a PLL

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To toggle something we need a clock reference. In our cheap FPGA board we have 50 Mhz reference clock as shown in the image below. But this clock should not be used directly but we can use a PLL to make a stable clock out of this reference. With PLL we also get the flexibility to increase or decrease the clock frequency. Altera (Intel) FPGAs provide an IP for PLL. You can use the IP from IP catalog. Usually on the Right Side pane. as shown below

Double click on ALTPLL and Save IP with a name. In our case we keep it simple and name it pll and press Ok

This should open a MegaWizard Plug-in Manager as shown below.

In the field What is the frequency of the inclk0 input? put the clock reference of your board. Please check the schematics and also check on which pin is it connected as this information will be needed later. For my board it is 50 Mhz.

Press Next > button

Toggle off the Create areset input to asynchronously reset the PLL and Create 'locked' output fields as we do not need it for out current use case.

We need to skip all Clock configurations except clk c0 by pressing Next > button. Till you reach the Summary page

On Summary page click on toggle button pll.bsf, pll_inst.v and pll_bb.v as shown below

And finally press Finish button

This should create a pll symbol file for you that can be imported later.

Now right click in the Block Diagram and insert the PLL as shown below:

Create a PLL

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Similarly you need to insert input and output pins as shown below:

Then connect the pin to input of PLL as shown below:

Pin Planner

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Once you have connected input and output pins to the PLL input and output ports you can run compile with pressing CTRL+L or press the PLAY key on top menu bar or in the menu processing --> Start Compilation. You can also change the name from pin_name1 to any name you want as I have changed it to clk_input and Out_pin. Once the compilation finsih without any Errors we need to connect our software pins clk_input and Out_pin to real pin on the FPGA. There are different ways this can be achieved I will be using Pin Planner. On the top menu bar you see the Pin Planner icon

Press the icon and it should open the pin planner according to your FPGA version and package. Now the important bit comes into play and you need to know where your clock reference pin is connected on the FPGA and where do you want to connect your Out_pin to. I have decided to connect my Out_pin to PIN_L6 which can be found from the Grid layout, Column 6 and Row L. There is no particular reason to select this Pin but in future we might decide it based on some other factors that I will discuss in future blogs. My clk_input is constraint by Hardware design of the board hence need to be used as written in datasheet of the board which is PIN_E16. See Schematic. You can assign pin by clicking on the pin and setting the pin to your soft pin as shown below:

You need to also change the pin I/O Standard to 3.3-V LVTTL or check hwat voltage is used for particular Pin in I/O Bank. This topic will be handled in latter blogs.

Once you have signed both pin. Just close the Pin Planner and re-compile the whole program.

Now we can upload out bit file to the FPGA.

USB-Blaster JTAG Programmer

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Before you insert you USB-Blaster you might need to give root privileges to your USB-Blaster debugger if you are using linux (Ubuntu 22.04). You can add a rule in /etc/udev/rules.d/92-usbblaster.rules to add a rule you ned to edit the file. Open this file with your favorite editor with sudo or root privilege. I am using vim.

sudo vim /etc/udev/rules.d/92-usbblaster.rules

and insert flollowing text

# USB-Blaster
SUBSYSTEM=="usb", ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6001", MODE="0666"
SUBSYSTEM=="usb", ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6002", MODE="0666"

SUBSYSTEM=="usb", ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6003", MODE="0666"

# USB-Blaster II
SUBSYSTEM=="usb", ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6010", MODE="0666"
SUBSYSTEM=="usb", ATTRS{idVendor}=="09fb", ATTRS{idProduct}=="6810", MODE="0666"

Click on programmer icon on the top Then Go to Hardware Setup and select the USB-Blaster[1-X] and Mode JTAG. Add file that has name Test.sof inside your project folder and output_files folder it should look something like figure shown below:

Press the start button and it should show succesful flashing of FPGA.

Testing the GPIO toggle

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I have set my PLL frequency to 20 MHz and connected my Saleae Logic analyzer to PIN_L6 on the board. And I get a clean 20 Mhz signal as shown below:

I can also increase the PLL frequency to change the toggle frequency.

In the future blogs I will be creating more complex FPGA projects. Where we use communication between a Raspberry Pi and FPGA and make something awesomazing.