FPGA - Zero to Hero: Vol 1

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Welcome to this introductory guide on FPGAs—a journey from the basics to hands-on programming. This article covers the essentials of Field Programmable Gate Arrays, the companies behind them, the languages used for programming, and step-by-step instructions on getting started with your first Verilog code and flashing designs onto popular FPGA platforms.

What is a FPGA

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A Field Programmable Gate Array (FPGA) is a semiconductor device that contains an array of programmable logic blocks and a hierarchy of reconfigurable interconnects. Unlike fixed-function integrated circuits, FPGAs can be reprogrammed to implement a wide range of digital functions after manufacturing. Key characteristics include:

• Flexibility: Customizable hardware configuration to meet specific application requirements.
• Parallelism: Ability to perform multiple operations simultaneously, making them ideal for high-speed processing tasks.
• Rapid Prototyping: Quick iteration cycles for developing and testing digital logic designs.

What all Companies Make FPGAs

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Several companies are involved in manufacturing of FPGAs, manufacturing devices that cater to diverse applications from consumer electronics to aerospace systems. Major players are:

• Xilinx (AMD): Link
• Intel (Altera): Link
• Lattice Semiconductor: Link
• Microchip (formerly Microsemi): Link
• QuickLogic: Link

What Language Can Be Used To Program Them

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Programming FPGAs is fundamentally different from writing software for a CPU. The primary languages and methods include:

• Hardware Description Languages (HDLs):
  • Verilog: Widely used for digital circuit design and simulation.
  • VHDL: Another popular HDL, favored in many academic and industrial settings.
• High-Level Synthesis (HLS):
  • Tools that allow designers to write in higher-level languages like C/C++ and automatically convert code into hardware descriptions. In later blogs I will also tackle how to do High level synthesis
• SystemVerilog/SystemC: Extensions to traditional HDLs that support system-level design and verification.

These languages allow hardware engineers to describe the behavior of hardware and design software led Hardware designs.

Sequential Execution Vs Hardware Description

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Understanding the difference between sequential execution and hardware description is crucial when moving from traditional programming to FPGA design:

Sequential Execution (Software): Sequential Execution software/program execute one instruction at a time in a linear sequence. Like a pathways A -> B -> C. Sometimes you jump to another path and it continues there after.

It is suitable for general-purpose processors where tasks are handled sequentially. Programming languages like C/C++, ASM , Java , Rust all are designed in this ways. That how processor and human understand and interact with each other.

int main(){
  int a = 1; // executed 1
  int b = 2; // executed 2
  int c = a + b; // executed 3
  ...
}

Hardware Description (FPGAs): Hardware Descriptive code describes circuits where multiple operations occur simultaneously.

It emphasizes parallelism and every module n block operates concurrently. Design is more about defining data paths, gates and signal interactions rather than writing step-by-step instructions that happens sequentially.

This distinction means that while software development focuses on algorithms and control flow, FPGA design is about configuring hardware to perform tasks in parallel, offering significant performance advantages for the right applications.

Stepping stone for Verilog Code

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Let’s dive into your first piece of Verilog code and try to understand the basics. Here’s a simple example that implements an AND gate:

// Define a module named 'and_gate'
module ANDgate (
    input wire a,  // First input
    input wire b,  // Second input
    output wire c  // Output that represents the logical AND of a and b
);
  
    assign c = a & b; // c wire is connected to output of and gate with wire a  and  b connected to as input
endmodule

Going through this code first line we encounter is module name. This is template of the module we want to create. inside are all the connections input and output defined. This module has 3 connection 2 input wires and 1 output wire

second line is assignment operation where assign keyword is used to assign wire c with and operation of wire a and wire b

Lets Write test to verify this gate

`timescale 1ns/1ps
module ANDgate_tb;
  reg a, b;
  wire c;
  
  ANDgate ut (.a(a), .b(b), .c(c));
  
  initial begin
    $monitor("At time %t: a = %b, b = %b, c = %b", $time, a, b, c);
  end
  
  initial begin
    $dumpfile("ANDgate_tb.vcd");
    $dumpvars(0, ANDgate_tb);

    // Test case 1: a = 0, b = 0 -> Expected c = 0
    #10; a = 0; b = 0;
    // Test case 2: a = 0, b = 1 -> Expected c = 0
    #10; a = 0; b = 1;
    // Test case 3
    #10; a = 1; b = 0;
    // Test case 4
    #10; a = 1; b = 1;
    $finish;
  end

endmodule

As you can see this test is also written in verilog but has different syntax.verilog has synthesizable and non-synthesizable syntax. commands like $dumpfile, $dumpvars and $display and $monitor are non-synthesizable. That means it doesnt generate any hardware. Here we are simulating our unit under test instance ut with multiple input and trying to test the output.

Install Verilog compiler and Testbench visualization

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In Ubuntu 22.04

sudo apt-get install iverilog gtkwave

To compile the code and simulation just save hardware description as ANDgate.v and Test bench as ANDgate_tb.v

and in terminal where the files are run following command:

iverilog -o ANDgate ANDgate.v ANDgate_tb.v 

To generate a simulation out of this we need to run another tool call vvp

vvp ANDgate

this should generate a ANDgate_tb.vcd file that can be loaded into GTKwave

gtkwave ANDgate_tb.vcd

Now you can visualize all the test signals and outputs

In future blog post I will continue the journey to flash this gate on a Hardware